(Answered): 3.8 The transistor-level circuit below implements the logic equation given below. Label the inputs ...

3.8 The transistor-level circuit below implements the logic equation given below. Label the inputs to all the transistors. Y-NOT (A AND (BOR C) 3.9 Fill in the truth table for the logical expression NOT(NOTEA) OR NOT(B)). What single logic gate has the same truth table? NOTINOT(A) OR NOTB A 0 0 1 B 0 1 0 3.10 Fill in the truth table for a two-input NOR gate. A NORB ? 0 0 1 1 B 0 1 0 1 3.13 How many output lines will a five-input decoder have? 3.14 How many output lines will a 16 input multiplexer have? How many select lines will this multiplexer have? 3.15 If A and B are four-bit unsigned binary numbers, 0111 and 1011. complete the table obtained when using a two bit full adder from Figure 3.15 to calculate each bit of the sumn, S. of A and B. Check your answer by adding the decimal value of A and B and comparing the sum with S. Are the answers the same? Why or why not? 0 1 1 0 1 1 0 1 1 A A $ Cou 3.16 Given the following truth table, generate the gate-level logic circuit using the implementation algorithm referred to in Section 3.3.4. Z 1 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 ? 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 3.23 Given the logic circuit in Figure 3.38, fill in the truth table for the output value Z Z A 0 0 0 0 1 1 ! 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 4 ? Figure 3.38 D'agram for Exercise 3.23