(Answered): Verilog code for main module and testbench 1. Write a Verilog code for a 4-bit Ring Counter with a p ...

1. Write a Verilog code for a 4-bit Ring Counter with a positive edge clock as described in the figure. D Q3 D D Q D QO >CLK CLK CLK >CLK Q Q. CLOCK ???? 2. Write a Verilog code for a 4-bit Johnson Ring Counter with a positive edge clock. For example 1000,1100,1110,1111,0111,0011,0001,0000 D DCLK CLK CLK CLK CLOCK Deliverables: 1. Verilog code for main module and testbench as well. (you can copy paste it on the document or attach the .v file 2. Screenshot of TCL console showing the change in the output (using $monitor command) 3. Screenshot of timing chart that pops up after running the behavior simulation